Investigating Split Locks on x86-64

This article analyzes split lock performance issues on x86-64 processors across multiple CPU architectures. Split locks occur when atomic operations cross cache line boundaries, forcing CPUs to use slow bus locks that disrupt system-wide memory performance. The author benchmarks Arrow Lake, Zen 5, Alder Lake, Zen 2, Skylake, Piledriver, and Goldmont Plus to show how severely split locks degrade latency and bandwidth beyond L2 caches.